81 results for Design Verification Engineer Jobs in Campbell, CA, US

Minimum qualifications:Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.2 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based Integrated Circuits (ICs) and chips.E...

Design Verification EngineerEtched is building the hardware for superintelligence.GPUs and TPUs are flexible AI chips that can run many kinds of models: CNNs, RNNs, LSTMs, and more. But today, almost all AI workloads, from ChatGPT to self-driving cars, are done on one model architecture: transformer...

Pay rate range: $85/hr to $107/hr on W2.Job description:• Looking for 8+ years SystemVerilog UVM experience, IP design verification and formal verification.THE ROLE:We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant suc...

About GroqGroq delivers fast, efficient AI inference. Our LPU-based system powers GroqCloud™, giving businesses and developers the speed and scale they need. Headquartered in Silicon Valley, we are on a mission to make high performance AI compute more accessible and affordable. When real-time AI is ...

CompanyQualcomm Technologies, Inc.Job AreaEngineering Group, Engineering Group > ASICS EngineeringGeneral SummaryQualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich ...

Responsible for verifying complex digital designs, planning verification of design blocks, creating verification environments using SystemVerilog and UVM, and collaborating with design engineers to debug and close coverage measures.

LocationSan Jose / Austin, USAExperience3-4 yearsSalary RangeMarket CompetitiveDesign Verification EngineerFull TimeJob DescriptionWe are looking for a team player with solid technical skills to add to our core engineering team. Candidates must have a strong technical background and be capable of co...

Responsible for the complete verification lifecycle including pre-silicon test planning, developing testbenches using SystemVerilog-UVM, coverage and assertion model development, and automation for verification efficiency.

Role: Design Verification Engineer (Not mre than 14 years profile)Location: Mountain View, CA (working from Google office)5 to10 years - 10 to 14 years- C2C fine Key ResponsibilitiesStrong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs a...

Job DetailsJob Description:Join Intel and build a better tomorrow. Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us and help us create the next generation of technologies ...