Design Verification Engineer

Etched is building the hardware for superintelligence.

GPUs and TPUs are flexible AI chips that can run many kinds of models: CNNs, RNNs, LSTMs, and more. But today, almost all AI workloads, from ChatGPT to self-driving cars, are done on one model architecture: transformers. Using flexible AI chips for transformers is very inefficient: <5% of the transistors on an H100 are used for matrix multiplication!

Etched is building a single-purpose chip exclusively for transformer inference. We only support transformers, but in exchange our chips have an order of magnitude more throughput and lower latency than an H100. With Etched, you can build products that would be impossible with GPUs, like tree-of-thought agents and ultra-low-latency audio chat bots.

We are seeking highly motivated Principal Verification Engineers to join our team. Our verification This role will report to the VP of Hardware Engineering.

Responsibilities:

• Ensure shippable first silicon for Etched’s first ASIC.
• Develop test benches for blocks and IP.

Requirements:

• At least 2 years of relevant experience developing scalable test benches.
• Proven understanding of System Verilog testbench language.
• Experience with high speed SerDes.
• Willing to start quickly.
• Passionate about modern AIs like ChatGPT, and willing to learn about them on the job.

Desired qualifications:

• Experience with chip-to-chip interconnects and HBM3/HBM3E technologies.
• Familiarity with transformer models and machine learning.
• Familiarity with numerical representations and functions.
• ​Ability to program with Python or another scripting language.
• Familiarity with open-source verification tools like Verilator.

Benefits

• Full medical, dental, and vision packages, with 100% of premium covered
• Housing subsidy of $2,000/month for those living within walking distance of the office
• Daily lunch and dinner in our office
• Relocation support for those moving to San Jose

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.