AppLab Systems, Inc

Design Verification Engineer

Mountain View, CA, US

about 1 month ago
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Summary

Role: Design Verification Engineer (Not mre than 14 years profile)

Location: Mountain View, CA (working from Google office)

5 to10 years -

10 to 14 years-

C2C fine

Key Responsibilities

  • Strong understanding of SV and UVM and good debugging skills.
  • Understanding of AMBA protocols.
  • Understand design specs and develop test plans based on functional and architectural requirements
  • Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing
  • Develop directed and random testcases, perform coverage analysis, and close functional/code coverage
  • Debug simulation failures and work closely with RTL designers to resolve issues
  • Execute regression runs, analyze results, and contribute to continuous improvements
  • Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed
  • Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains
  • Document test environments, test plans, and results for internal and external reviews

Have a Great Day!

Warm Regards,

Mohit Mittal

Lead Recruiter

Contact Details: 609-629-2040

Email: [email protected]

4365 Route 1 South, Suite 105

Princeton, NJ 08540

www.applabsystems.com

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