Vertisystem is Hiring for a Design Verification Engineer who can use their verification skills to define verification requirements, create test cases, design and implement the testing infrastructure, execute the testing, and report the results for the new product designs.

Skills:

Must have atleast 3+ years of experience with Verification methodologies and languages such as UVM and System Verilog

Experience owning areas of product verification

Working knowledge of C#, Python, and LabVIEW

Experience with firmware verification

Experience in gate-level simulations and low power (UPF) verification is a plus

Experience in silicon bring-up activities is advantageous