8 results for Digital Verification Engineer Jobs in Mountain View, CA, US

Pittsburgh, PA or San Jose, CAFull-TimeEngineeringDesign VerificationEfficient is looking for a Digital Verification (DV) Engineer who wants to influence the next computing revolution. We are seeking an engineer with industry experience to help us in our verification efforts for our first-generation...

Quantum computing holds the promise of humanity’s mastery over the natural world, but only if we can build a real quantum computer. PsiQuantum is on a mission to build the first real, useful quantum computers, capable of delivering the world-changing applications that the technology has long promise...

Position: Design Verification EngineerLocation: Austin, TX / San Jose, CADuration: Long-termJob Description:Develop reusable testbenches from scratch using SystemVerilog and UVM.Perform gate-level simulations (GLS), debug timing-related issues, and generate power vectors.Drive verification best prac...

Siemens EDA Business is a global technology leader in electronic design automation software. Our software tools enable companies around the globe to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technolog...

Responsible for developing test plans and test benches, running and debugging regression tests, and collaborating with hardware and software teams to validate functionality. Requires experience with UVM, System Verilog, and scripting languages like Python.

Responsible for creating constrained-random verification environments to ensure the functional correctness of programmable chips, particularly in verifying Ethernet, TCP/IP, and networking blocks. Requires extensive experience in ASIC/SoC verification and knowledge of verification flows and methodol...

Responsible for writing and understanding assembly language for testing RTL, debugging assembly level failures, and conducting coverage analysis. Requires knowledge of processor internals and micro-architecture level understanding of RTL.

Responsible for system verification of SOC architecture, developing UVM testbenches, and working with AMBA bus protocol standards. Experience in hardware security is desirable.