Job Description:1) Central to our mission is a highly programmable chip. As part of the verification team, you will be responsible for independently creating leading edge constrained-random verification environments and using them to drive functional correctness of innovative designs. Key Qualifications BS in Electrical Engineering or equivalent degree 10+ years of experience in ASIC/SoC verification with SV/UVM environments In-depth knowledge of verification flows Clear understanding of constrained random verification process, functional coverage, assertion methodology & philosophy Team player with excellent communication skills and the desire to take on diverse challenges Experience in verifying Ethernet, TCP/IP, networking blocks, specifically MAC/PCS blocks Additional Success Factors Advanced knowledge of CPU, Cache Hierarchy, & SoC architecture/design Experience in verifying PCIe and other industry standard protocols Experience with modeling in C/C++ Knowledge of formal verification, hardware emulation