551 results for Design And Verification Engineer Jobs

Responsible for advanced UVM based test bench development and debugging, defining and executing RTL verification tests, performance and power-aware verification, debugging RTL designs in Verilog and System Verilog, and improving verification processes. Requires expertise in complex SoC projects and ...

Pay Rate: $86 Hourly on W2 all inclusiveJob Description:We are looking for an adaptive, self-motivative Design Verification Engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve CLIENT's abilities to deliver the highest quality, industry-lea...

Pay rate range: $85/hr to $107/hr on W2.Job description:• Looking for 8+ years SystemVerilog UVM experience, IP design verification and formal verification.THE ROLE:We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant suc...

CompanyQualcomm Technologies, Inc.Job AreaEngineering Group, Engineering Group > ASICS EngineeringGeneral SummaryQualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich ...

The Role The focus of this role is to plan, build, and execute the verification of new and existing features for our custom silicon/ASIC designs, resulting in zero bugs in the final design to ensure first time silicon success.THE PERSON:You have a passion for modern, complex processor architecture, ...

Responsible for the complete verification lifecycle including pre-silicon test planning, developing testbenches using SystemVerilog-UVM, coverage and assertion model development, and automation for verification efficiency.

Develop and manage verification and test environments for state-of-the-art chip designs, define verification test plans, verify design functionality through scalable testbenches, and perform integration level testing. Integrate IPs into testbenches, develop regressions, and conduct functional bringu...

Responsible for all phases of pre-silicon verification including establishing DV methodology, developing test-plans and verification environments, writing tests, debugging, and ensuring bug-free first silicon for SoC/IP designs. Develops verification plans, executes them, and tracks DV progress usin...

Job DetailsJob Description:Join Intel and build a better tomorrow. Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us and help us create the next generation of technologies ...

Responsible for planning verification of complex digital design blocks, creating comprehensive verification test plans, designing testbenches in System Verilog and UVM, debugging tests with design engineers, and performing coverage analysis to improve stimulus quality.