Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Senior Verification Engineer to be driving into the complicated RTL design verification activity on various design aspects. Requirements Requirements * 6+ years of experience - a must * Performed at last 2 or more full block/system verification cycles. * In depth knowledge in VLSI verification flow, languages and concepts. * Experience in data path or data protocols, specifically Ethernet - preferred * Verification using one of the known methodologies (eRM, UVM, OVM). Responsibilities * Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers. * Build verification environments using SystemVerilog and UVM. * Identify and write all types of coverage measures for corner-cases. * Debug the functionality with design engineers. * Perform coverage collection and follow the metrices to close the full functionality.