Senior Verification Engineer - Digital Design Verification - High-Speed Communication Protocols - Austin - UVM - DSP

We are partnered with a rapidly growing fabless semiconductor startup that is creating novel DSP technology to revolutionize AI infrastructure and cloud connectivity as they build a new team in Austin, TX.

If you are experienced within digital design verification engineering and looking for a new challenge in a dynamic, fast-paced environment, then I want to speak with you!

Role: Senior Verification Engineer

Salary: $160,000 - $175,000 + equity options

Location: Austin, TX

The skills needed for the role include:

• 6 plus years' experience working within digital design verification positions.
• Extensive knowledge of VLSI verification flows, concepts and methodologies.
• Successfully completed two or more full block/system verification cycles through to tape-out.
• Expert in industry standard verification methodologies - UVM, SystemVerilog.
• Experienced with high-speed communication protocols - Ethernet, SerDes, PCIe.
• Knowledge / experience of one of the verification methodologies (UVM, OVM, eRM).
• Driven, enthusiastic individual that is ready for a new challenge, in a fast-paced, dynamic environment that will have a profound impact on the future of optical communication technology.

If you are interested in the Senior Verification Engineer opportunity, apply directly to this advert for immediate consideration.

Alternatively, please contact Andre Paz at [email protected] for further details!