We are seeking highly skilled Design Verification Engineers to join our team. In this role, you will be responsible for defining and implementing verification plans, developing functional tests, and driving the verification process to closure. You will collaborate closely with cross-functional teams to ensure the highest design quality.

• Define and implement IP/SoC verification plans and build verification test benches.
• Develop functional tests based on verification test plans.
• Drive Design Verification closure using defined metrics, including test plan, functional, and code coverage.
• Debug and resolve functional failures in the design in partnership with the design team.
• Work with design, modeling, emulation, and silicon validation teams to ensure the highest design quality.
• B.S or M.S in Electrical Engineering, Computer Engineering, or Computer Science.
• Strong experience in Verilog, SystemVerilog, C/C++, and UVM methodology for verification.
• Hands-on experience in IP/sub-system and/or SoC level verification using SystemVerilog UVM/OVM methodologies.
• Experience with EDA tools and scripting languages such as Python, Perl, Shell for verification environments.
• Expertise in architecting and implementing design verification infrastructure and executing the full verification cycle.

Preferred Qualifications:

• Experience developing UVM-based verification environments from scratch.
• Knowledge of design verification for Data-center applications such as Video, AI/ML, and Networking.
• Familiarity with revision control systems like Mercurial (Hg), Git, or SVN.
• Experience verifying ARM/RISC-V-based sub-systems or SoCs.