The Self-Driving hardware team is looking for a SOC Verification Engineer who will be responsible for pre-silicon RTL verification of block and top-level SOC. With a strong knowledge of SOC architecture and SOC verification methodologies you will interact with multiple teams and build a metric-driven, configurable and flexible verification environment. * Work with team members to define and set up an SOC-level verification environment * Architect highly reusable UVM based test benches and integrate complex multi-instance VIPs, sub-system test benches and test suites at the SOC level * Achieve targeted coverage, work with design, architecture, SW, FW and external IP delivery teams to efficiently integrate and verify the design * Create coverage driven verification plans from specifications. Execute review and refine to achieve coverage targets * Define and review verification and validation test plans created by other members of the team * Post-silicon validation and SOC bring-up * Understand details of High Efficiency SOC Architecture, standard SOC peripherals and I/O(e.g. DDR, PCIe, USB), DMA, memory management schemes, multi-processor systems, Memory Controller Sub Systems, PLL, power up, Secured Boot schemes * 1+ years of dedicated/hands-on DV experience * Strong programming skills UVM, C/C++, Python/Perl * Experience verifying CPU/GPU integration at the SOC level * Coherency verification at the SOC level * Emulation experience, working on available platforms such as Palladium, or Zebu * Experience in SOC bring-up and post-silicon verification * Post-silicon validation and SOC bring-up * Hands-on verification experience with at least three of the following: NOC, PCIe, Bus Fabric, AHB, AXI, based bus architecture in UVM environment * Experience working on UPF integration, boot-up, HW/FW interaction verification * Reset and power verification