Essential Duties and Responsibilities: : Planning the verification of complex digital systems Creating a constrained-random verification environment using System Verilog and UVM Identifying and writing all types of coverage measures for stimulus and corner-cases Debugging tests with design engineers to deliver functionally correct design blocks Closing coverage measures to identify verification holes and to show progress towards tape-out Tools: VCS, URG, Verdi, System Verilog, Verilog, UVM, DVE Education Requirements : Required : Bachelor's degree in Electronics Engineering