Senior Design Verification Engineer - UVM/System Verilog Job Title : Senior Design Verification Engineer (5+ Years Experience)Location : Bangalore / HyderabadExperience : 5+ YearsDomain : SoC/IP/ASIC VerificationNotice Period : Immediate to 30 DaysAbout The RoleWe are looking for a Senior Design Verification Engineer (5+ years) with expertise in IP and So...