93 results for Asic Verification Engineer Jobs in United States

Involved in ASIC design verification for Cisco's high-end switching products. Responsibilities include defining verification plans, developing verification environments, executing test plans, debugging, and participating in simulation model development and performance analysis.

Responsible for developing comprehensive formal testplans and complete formal verification sign-off of complex blocks. Collaborate with software, hardware, and design teams to ensure first-pass silicon success. Experience with formal verification methodologies and hardware description languages is r...

Responsible for ASIC design verification for high-end switching products, including developing simulation models, test plans, and performance analysis. Collaborates with hardware and software designers and vendors.

Responsible for developing comprehensive formal test plans and conducting formal verification sign-off of complex ASIC blocks. Collaborates with cross-functional teams in software, hardware, ASIC Design, Emulation, and Post-Silicon to ensure silicon success.

Develop test benches and tests for FPGAs and ASICs, assist in root-causing RTL bugs, develop verification models, and draft detailed test plans. Participate in test plan and coverage analysis of the block and SOC-level verification.

Responsible for implementing a verification environment for testing RTL against reference models, developing detailed test plans, writing tests in C/C++, running formal verification, and participating in system level verification using UVM and System C.

Waymo is an autonomous driving technology company with the mission to be the most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands o...

Responsible for verifying new silicon designs for Ethernet systems using constrained random design verification methodologies. Collaborates with worldwide design and architecture teams, involving all aspects of design verification while potentially providing technical leadership.

Involves verifying new designs for high throughput Ethernet solutions using constrained random verification methodologies with System Verilog and UVM. Collaborates with design and architecture teams on leading edge products and provides technical leadership in design verification.

Responsible for verifying new silicon designs for Ethernet systems, using constrained random verification methodologies with System Verilog and UVM. Collaborates with global design and architecture teams, and drives completion via coverage closure.