Job Title: Junior Verification Engineer

Job Overview:

We are seeking a motivated and detail-oriented Junior Verification Engineer to join our digital hardware verification team. The ideal candidate will have foundational experience in UVM-based verification and a passion for embedded systems and hardware design. This role offers the opportunity to work alongside senior engineers in developing robust verification environments and test strategies.

Key Responsibilities:

• Collaborate with senior engineers to define and implement UVM-based verification plans for FPGA and ASIC designs.
• Develop and maintain SystemVerilog testbenches, test cases, and automation scripts.
• Perform functional and regression testing of digital hardware components.
• Analyze simulation results, identify bugs, and assist in debugging and issue resolution.
• Document verification procedures, test results, and track defects using standard tools.
• Ensure designs meet industry standards and project-specific requirements.
• Stay current with evolving verification methodologies and tools to continually improve processes.

Qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Basic understanding of SystemVerilog and the Universal Verification Methodology (UVM).
• Hands-on experience with C/C++ in the context of verification or embedded systems.
• Familiarity with scripting languages such as Python or Perl for automation tasks.
• Exposure to simulation tools like ModelSim, QuestaSim, or similar.

Desired Skills:

• Strong analytical and problem-solving skills with a keen eye for detail.
• Effective communication and teamwork skills in a collaborative engineering environment.
• Enthusiastic learner with the ability to adapt to new technologies and methodologies.