We’re Hiring | Senior Design Verification Engineers | Pan India

Are you a passionate DV engineer looking for your next big opportunity? Join our team of innovators driving the next generation of semiconductor solutions!

We are looking for Senior Design Verification Engineers with strong experience in ASIC/IP/SoC verification for multiple locations across India. If you’re ready to work on cutting-edge projects and collaborate with top talent across the industry, we’d love to connect!

Role: Senior Design Verification Engineer

Location: PAN India (Travel to UK within 3-6 months / UK work permit Visa associates can apply)

Experience: 7-11 years of exp

Responsibilities:

• Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification)
• Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage
• Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality
• Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues
• Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence
• Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment
• Participate in code reviews and champion best practices for verification code quality
• Stay current with the latest advancements in verification tools and methodologies

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)
• 7-11 years of solid experience in Design Verification for ASICs or SoCs
• In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines)
• Proven ability to develop, debug, and optimize complex verification environments
• Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal)
• Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl)
• Experience with formal verification tools and techniques is a plus
• Excellent analytical and problem-solving skills with a meticulous attention to detail
• Strong communication, collaboration, and leadership skills to effectively contribute and guide the team.