Job Description:
Job Summary:
We are looking for a highly experienced and motivated Senior Design Verification Engineers with a deep understanding of the PCIe protocol and hands-on experience in System Verilog and UVM. The ideal candidate will lead verification activities for complex PCIe subsystems or SoCs, and contribute to building scalable, reusable verification infrastructure.
Key Responsibilities:
Required Skills & Experience:
Nice to Have:
Soft Skills: