Senior ASIC Design Engineer - IP development

A leading innovator in secure silicon IP is seeking an experienced ASIC Design Engineer to join their cutting-edge R&D team based in the Netherlands. This is a unique opportunity to contribute to the development of high-performance, security-focused semiconductor solutions used in data-intensive environments.

In this role, you’ll play a key technical role with hands-on involvement in both digital architecture and RTL block-level design. Working within a collaborative R&D environment, you’ll contribute to the development of advanced silicon IP alongside experienced engineers.

Ideal Candidate:

• Degree-qualified in Hardware Engineering, Computer Science, or related discipline (BSc, MSc or equivalent).
• Proven experience in 5+ successful tapeouts
• Define and develop RTL blocks as part of secure and complex ASIC designs.
• Own block-level design from architecture through to implementation and delivery.
• Work closely with system architects to align block functionality with top-level design goals.
• Experience with IP delivery, hand-off processes, and technical documentation
• Proficient in Verilog, VHDL, and/or SystemVerilog, with a strong understanding of synthesis, lint, CDC, and related flows.

Email - [email protected]

Tel - 01189073075

LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/