4-8 Yrs Implementation with emphasis on Physical Verification & project finishing/tapeout activities.
Expertise
Excellent understanding of Physical Verification flow with in-depth experience in analysing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues (mostly working on ICV and Calibre tools ).
Good handson/understanding, debug skills and fixing techniques preferred for base drc, metal drc, double/triple patterning layers in latest tech nodes.
Good handson LVS/antenna runs/debug/fixes along with runtime reduction using LSF resources.
Good understanding and handson on scripting skills in Unix, Perl, Python and Tcl to enable good quality and ontime tapeouts.
Understanding of ESD, latch-up etc.
Own and execute PV activities at the block level.
Work closely with PD team in addressing their PV issues and suggest solutions to them.
Good understanding of full chip integration and flows is a plus.
Innovus level DRC fixing is a plus.
Skill Set
Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc.
Experience in PnR tools like ICC/Innovus with regards to physical convergence must.
Good handson/understanding, debug skills and fixing techniques preferred for base drc, metal drc, double/triple patterning layers in latest tech nodes.
Good handson LVS/antenna runs/debug/fixes along with runtime reduction using LSF resources.
Good understanding and handson on scripting skills in Unix, Perl, Python and Tcl to enable good quality and ontime tapeouts.
Hands on experience :Innovus/Fusion Compiler , Tech lef is preferable.
(ref:hirist.tech)
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