Job Title: Senior/Lead/Manager – SoC Design Verification Engineer

Job Description:

• We are looking for a highly skilled SoC Design Verification Engineer at the Senior, Lead, or Manager level to define and drive verification methodologies, ensure the functional correctness of complex SoCs, and contribute to the development of cutting-edge semiconductor technology. The ideal candidate will have deep expertise in verification processes, industry-standard tools, and automation techniques while collaborating with cross-functional teams to deliver high-performance SoC solutions.

Key Responsibilities:

• Define and implement SoC verification strategies and methodologies to ensure functional correctness and high-quality silicon.
• Develop test plans, test benches, assertions, and coverage models to validate complex SoC designs.
• Work with multiple verification platforms, including UVM test benches, emulators, and software-based environments.
• Debug system-level issues, identify architecture, functional, and performance-related bugs, and ensure SoC functionality meets specifications.
• Collaborate with cross-functional teams (Product Design, Computer Vision, Audio, Hardware, Software) to define and execute verification architecture.
• Develop directed and constrained-random tests, analyze coverage metrics, and drive verification closure.
• Optimize test infrastructure and automation using scripting languages like Python, Perl, and TCL.
• Work with industry-standard IO interfaces (AMBA, CXL, USB, MIPI, PCIe, DDR, etc.) to verify SoC subsystems.
• Leverage formal verification techniques to enhance verification efficiency.
• (Lead/Manager level): Mentor junior engineers, manage verification teams, and drive strategic improvements in verification methodologies.
• (Manager level): Define and own verification roadmaps, establish best practices, and ensure high-quality SoC validation for successful tape-out.

Qualifications & Skills:

• Bachelor’s/Master’s degree or higher in Electrical Engineering, Electronics & Communication (EEE/ECE), or a related field.
• 7+ years (Senior), 10+ years (Lead), 12+ years (Manager) of semiconductor design verification experience with expertise in:
• SystemVerilog, UVM, GLS, assertions, and coverage-driven verification.
• Developing test plans, test benches, and automated verification flows.
• Debugging system-level issues and identifying functional/architectural bugs.
• SoC-level verification, including processor (ARM/RISC-V) and full-system testing.
• Working with industry-standard tools for verification, simulation, and debug.
• Formal verification methodologies for enhanced verification completeness.
• Strong knowledge of IO interfaces (AMBA, CXL, USB, MIPI, PCIe, DDR, etc.).
• Experience in SoC architecture and system-level debug is a strong plus.
• Proficiency in scripting languages (Python, Perl, TCL) for automation.
• Excellent verbal and written communication skills, with the ability to collaborate across multi-disciplinary teams.

This role offers an exciting opportunity to lead, contribute, and drive innovation in the verification of state-of-the-art SoC designs. If you are passionate about hardware verification and developing world-class semiconductor solutions, we’d love to hear from you!