Full time

New Cairo, Egypt

29/01/2024

DD_203

Job Description

• Implement new standards and algorithms from the ground up
• Design and build an entirely new flow
• Assemble and lead a talented team of engineers, fostering a culture of creativity, collaboration, and technical excellence
• Develop a thorough understanding of system-level design specifications
• Verilog RTL Coding, Synthesis, Simulation of the digital IPs
• Working with the verification team to develop advanced test plans
• Static timing analysis and timing closure
• Hardware verification of the digital module using cutting edge FPGA kits
• Contribute to the validation and debugging of the fabricated silicon
  
  

Job Requirements

• B.Sc. or M.Sc. in Electronics Engineering
• 5+ Years of experience in Digital Design
• Technical leadership and project management skills
• Expert knowledge in Verilog RTL coding techniques
• Strong Knowledge of ASIC/FPGA design flows including RTL synthesis, and timing closure of high speed digital designs
• Experience with clock domain crossing and reset architecture
• Knowledge of System Verilog, RTL/gate verification techniques
• Strong knowledge of Shell, Perl, Python and TCL scripting