Title: Design Verification Engineer

Experience: 4

Description:

Experience in verification of DDR/PCIe/USB/Ethernet protocols

Strong knowledge of verification methodologies (UVM/OVM)

Proficiency in Verilog/VHDL and SystemVerilog

Expertise in using simulation tools such as ModelSim, VCS, etc.

Experience with protocol-specific tools (e.g., PCIe compliance test tools, DDR protocol analysis, etc.)

In-depth understanding of digital design, timing analysis, and debugging skills

Focus on improving verification coverage and efficiency

Create and execute testbenches, ensure thorough verification of protocol functionality

Perform simulations and debugging to identify and resolve issues

Collaborate with the design team to ensure that the implementation meets specification requirements