Greetings From Canvendor!

Role: Design Verification

Location: Bangalore

Experience: 4+ years

Job Description:

• Extensive experience in executing IP verification or subsystem verification of complex blocks.
• Proficiency in SystemVerilog (SV), Universal Verification Methodology (UVM), assertions, testbenches, test plans, and coverage.
• Strong experience in verifying Fabric/NOC/Interconnect blocks.
• Knowledge of protocols such as AMBA suite (AXI/ACE), PCIe, CXL, interrupt handling, and power management.
• Experience or knowledge of coherent traffic verification is a plus.

Candidate Mandate:

• Ensure that experience and relieving letters are available for all employers listed in the resume and UAN history.
• If you find any minor discrepancies in the UAN history compared to the experience letters or resume, please inform us in advance with a proper justification.
• All selected candidates will undergo a UAN check before we roll out the offer. Therefore, ensure the above mandates are met to save our time.
• Candidates' experience will be counted after the completion of their graduation without backlogs.

if interested candidate kindly share your updated resume to [email protected]