Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications.Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. 5+ years of experience in static verification tools Experience with Lint, Clock Domain & Reset Domain crossing. Experience with SOC CDC signoff Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other HDL. Experience with communicating across functional internal teams and vendors. Experience with SOC Design Integration and Front-End Implementation. Knowledge of Timing/physical libraries, SRAM Memories. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools. Experience with Netlist-CDC Analysis and improving MTBF Experience with developing structural rule based checks for RTL & Netlist Scripting and programming experience using Perl/Python, TCL, and Make.