Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications.Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. 5+ years of experience with STA tools Experience with developing full chip flat & hierarchical timing constraints Experience with AOCV/POCV timing analysis , SI noise analysis Experience with running Static Timing Analysis for full chip using DMSA Knowledge of front-end and back-end ASIC flows Experience with communicating across functional internal teams and vendors. Experience with SOC Design Integration & Front End Implementation Experience with Front End Synthesis tools such as Design Compiler, Genus Experience with Back End PD tools such as Fusion Compiler, Innovus Experience with Understanding RTL design using SystemVerilog or other HDL. Experience with EDA tools and scripting languages (Python, TCL) used to build tools and flows Knowledge of Timing/physical libraries, SRAM Memories.