Role Description

ASIC Design Verification Engineer

Technical Lead I – VLSI

Who We Are

Born digital, UST transforms lives through the power of technology. We walk alongside our clients and partners, embedding innovation and agility into everything they do. We help them create transformative experiences and human-centered solutions for a better world.

UST is a mission-driven group of 29,000+ practical problem solvers and creative thinkers in more than 30 countries. Our entrepreneurial teams are empowered to innovate, act nimbly, and create a lasting and sustainable impact for our clients, their customers, and the communities in which we live.

With us, you’ll create a boundless impact that transforms your career—and the lives of people across the world.

Visit us at UST.com.

You Are

We are looking for an experienced and passionate ASIC digital design engineer with strong background in digital design verification. You thrive in a collaborative environment, working directly with analog and digital experts to create customized digital solutions.

The Opportunity

• Collaborating with System Architects, RTL Designers, Silicon Validation engineers, and other verification engineers to develop comprehensive verification strategies.
• Converting system specifications into detailed verification test plans.
• Ensuring that verification methodologies are applied across both digital and analog domains to achieve full coverage.
• Generating random and constrained random test patterns to validate functionality.
• Creating functional patterns to measure and ensure complete function coverage.
• Validating .lib and other digital views to guarantee accuracy and reliability.
• Drive the development of high-quality NVM products that meet stringent industry standards.
• Ensure comprehensive verification coverage, reducing the risk of functional errors in final products.
• Enhance the reliability and performance of Synopsys products through meticulous validation processes.
• Contribute to the successful integration of digital solutions in high-volume applications.
• Support the advancement of cutting-edge technology in the semiconductor industry.
• Foster a collaborative and innovative work environment, driving continuous improvement.
  
  

This position description identifies the responsibilities and tasks typically associated with the performance of the position. Other relevant essential functions may be required.

What You Need

• Bachelor’s or Master’s degree in Electrical Engineering or a related field.
• 10+ years of industry experience in digital ASIC design verification.
• Proficiency in verification planning and execution, with experience in UVM and System Verilog.
• Strong skills in writing and debugging test benches.
• Experience with RTL, Verilog, System Verilog, and scripting languages.
• Familiarity with tools such as Custom Compiler, Design Compiler, Fusion Compiler, VCS, Verdi, DVE, Z01X, Spyglass, VIP, FPGA Emulation, and UPF.
  
  

Compensation can differ depending on factors including but not limited to the specific office location, role, skill set, education, and level of experience. UST provides a reasonable range of compensation for roles that may be hired in various U.S. markets as set forth below.

Role Location: Remote

Compensation Range: $87,000-$131,000

Benefits

Full-time, regular employees accrue a minimum of 10 days of paid vacation per year, receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year), 10 paid holidays, and are eligible for paid bereavement leave and jury duty. They are eligible to participate in the Company’s 401(k) Retirement Plan with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance, as well as the following Company-paid Employee Only benefits: basic life insurance, accidental death and disability insurance, and short- and long-term disability benefits. Regular employees may purchase additional voluntary short-term disability benefits, and participate in a Health Savings Account (HSA) as well as a Flexible Spending Account (FSA) for healthcare, dependent child care, and/or commuting expenses as allowable under IRS guidelines. Benefits offerings vary in Puerto Rico.

Part-time employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year) and are eligible to participate in the Company’s 401(k) Retirement Plan with employer matching.

Full-time temporary employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year) and are eligible to participate in the Company’s 401(k) program with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance.

Part-time temporary employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year).

All US employees who work in a state or locality with more generous paid sick leave benefits than specified here will receive the benefit of those sick leave laws.

What We Believe

We proudly embrace the values that have shaped UST since day one. We build our culture of Humility, Humanity, and Integrity. These values inspire us to nurture a people-first, human centric culture that fosters belonging, prioritizes sustainable solutions, and keeps our people and clients at the forefront of all decisions.

Humility

We will listen, learn, be empathetic and help selflessly in our interactions with everyone.

Humanity

Through business, we will better the lives of those less fortunate than ourselves.

Integrity

We honor our commitments and act with responsibility in all our relationships.

Equal Employment Opportunity Statement

UST is an Equal Opportunity Employer.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, status as a protected veteran, or any other applicable characteristics protected by law. We will consider qualified applicants with arrest or conviction records in accordance with state and local laws and “fair chance” ordinances.

UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.

#UST

Skills

Design Verification,System Verilog,Scripting,Uvm