Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 3 years of experience verifying digital logic at RTL level using SystemVerilog or C/C++.
• Experience creating and using verification components and environments in standard verification methodology.
• Experience verifying digital systems using standard IP components/interconnects (i.e., microprocessor cores, hierarchical memory subsystems).
• Experience with scripting languages and software development frameworks.
  
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Science or equivalent practical experience.
• Experience in one or more of the following areas: Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, Clock and Power Controllers.
• Experience with Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL).
• Experience with performance verification of SOCs, pre-Silicon analysis and post-Silicon correlation.
• Experience with building verification methodologies that span simulation, emulation and FPGA prototypes.
  
  

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Plan and execute the verification of the next generation configurable Infrastructure IPs, interconnects and memory subsystems.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM.
• Develop cross language tools and verification methodologies.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct blocks and subsystems and close coverage measures to identify verification holes and to show progress towards tape-out.
  
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .