Description

• Design and develop image sensor technologies.
• Transistor level design of analog and mixed-signal circuits for CMOS Image Sensor such as asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence Virtuoso.
• Work on whole chip floorplan design and pad frame.
• Work on analog and mixed signal circuits layout design by Cadence Virtuoso, such as column array.
• Collaborate with layout engineer on whole chip layout integration and improvement by Cadence Virtuoso.
• Sub-blocks and whole image sensor readout circuit simulation by simulators such as Analog FastSPICE (AFS), Empyrean ALPS and NanoSpice.
• Design verification such as DRC, LVS, PERC check by using Siemens Calibre.
• Whole chip IR drop check by using Ansys Totem.
• Conduct script modification using Perl programming language.
• Collaborate with Digital Engineer to define and design the analog to digital interface.
• Collaborate with verification, process, test, and application engineers to debug, characterize and optimize performance of fabricated image sensors.
• Propose innovative and creative solutions along with new circuit R&D and be ahead of current technology.
  
  

Job Requirements

Master's degree in Electrical Engineering, Computer Engineering, or related fields with courses work in Digital VLSI circuits, Analog Electronic Circuit, and Power Electronics.

Must Possess The Following Skills

• VLSI circuit design and transistor performance characterization.
• Circuit design with Cadence Virtuoso.
• Circuit simulation using Virtuoso ADE Suite.
• Analog circuit schematic and layout design and verification.
• Analog and digital circuit design flow.
• Cadence digital design and verification tools.
  
  

Annual base salary for this role in California, US is expected to be between $151,091- $155,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.