35 results for Asic Verification Engineer Jobs in Sunnyvale, CA, US

About Ethernovia, Inc.Ethernovia is fundamentally changing how cars of the future are built by unifying in-vehicle networks into an end-to-end Ethernet system. Founded in 2018, we're inventing the future of automobile's communication! We are transforming automobiles' communication network to enable ...

DescriptionAmazon Web Services (AWS) internships are full-time (40 hours/week) for 12 consecutive weeks during summer. By applying to this position, your application will be considered for all locations we hire for in the United States.In Annapurna Labs we are at the forefront of hardware co-design ...

Involves verifying new designs for high throughput Ethernet solutions using constrained random verification methodologies with System Verilog and UVM. Collaborates with design and architecture teams on leading edge products and provides technical leadership in design verification.

DescriptionProject Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.The RoleBe part of Project Kuiper’s sub-team responsible for defining and imple...

ResponsibilitiesCollaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verificationBuild and maintain infrastructure/environment for automation verification of SoC architecture, function and performanceDevelop reusable testbench, con...

Minimum qualifications: + Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience. + 2 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based Integrated Circuits (ICs) and...

Responsible for verifying complex digital designs, planning verification of design blocks, creating verification environments using SystemVerilog and UVM, and collaborating with design engineers to debug and close coverage measures.

Responsible for the complete verification lifecycle including pre-silicon test planning, developing testbenches using SystemVerilog-UVM, coverage and assertion model development, and automation for verification efficiency.

Description Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. The Role: Be part of Project Kuiper's sub-team responsible for defining an...

**Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal Verification to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will be part of a t...