Company Description

Cranes Varsity, a division of Cranes Software International Limited, is the authorized partner of Texas Instruments, providing lab equipment services to engineering colleges and research firms across India.

Required Freelancers/Consultant Trainer for VLSI - Static Timing Analysis & Deep Submicron Synthesis

Requirement

Duration 10 Days

Mode - Offline

Location - Bangalore

Tools Required - Licensed version - Synopsis/Cadence tools ▪ (SpyGlass Lint, SpyGlass CDC, Design Compiler, Prime Time)

Job Description - VLSI - Deep Submicron Synthesis & Static Timing Analysis

Objectives • Understand SoC architecture and design flow. • Perform RTL linting and CDC checks. • Develop synthesis setup and apply timing constraints. • Run synthesis and generate optimized netlist. • Perform static timing analysis and resolve violations. • Analyze PVT corners and achieve timing closure. Pre-requisites ▪ Knowledge of Digital Electronics & Logic Design ▪ Familiarity with HDL languages (Verilog/VHDL) ▪ Exposure to Linux-based environments for EDA tools.

Software tools required ▪ Synopsis/Cadence tools ▪ (SpyGlass Lint, SpyGlass CDC, Design Compiler, Prime Time).

Day 1: VLSI Development Flow & EDA Tools (8 hrs) • Topics: • VLSI Technology Overview • IPs, Subsystems, and SoCs • SoC Design Flow: RTL → Synthesis → PnR → STA • EDA Tool Overview • Hands-On: • RTL block inspection walkthrough • Explore tool environment setup (e.g., Synopsys DC)

Day 2: RTL Synthesis - Concepts & Setup (8 hrs) • Topics: • RTL Linting & Clock Domain Crossing (CDC) • Synthesis Basics: Mapping, Constraints • Hands-On: • Run RTL linting (SpyGlass Lint/CDC) • CDC checks on sample modules

Day 3: RTL Synthesis - Advanced Topics (8 hrs) • Topics: • Clocking schemes, Reset handling • Synthesis optimization techniques • Constraints (SDC) and their application • Hands-On: • Create SDC files • Apply optimization directives and observe impact

Day 4: Introduction to Static Timing Analysis (8 hrs) • Topics: • What is STA? • Setup/Hold, Slack, Skew, Delay Models • Hands-On: • Analyze a synthesized netlist timing report • Visualize timing paths (e.g., setup/hold violations)

Day 5: STA Deep Dive (8 hrs) • Topics: • Path Classification: Launch/Capture • Timing exceptions: False Paths, Multi-cycle Paths • Clock Uncertainty and Jitter • Hands-On: • Add constraints to declare false and multi-cycle paths • Fix timing violations

Day 6: Timing Closure & Reports (8 hrs) • Topics: • Static Timing Reports: Analysis and Fixes • Derating, Clock Gating Checks • Area & Power considerations during STA • Hands-On: • Interpret timing reports • Use constraints to balance area/power/timing

Day 7: EDA Tool Scripting & Automation (8 hrs) • Topics: • Tool flow automation using Tcl scripting • Batch mode synthesis & STA automation • Hands-On: • Create a complete Tcl script for Synthesis + STA • Generate reports via script

Day 8: Day 8: RTL Synthesis Lab (8 hrs) • Hands-On: • End-to-End Synthesis of an IP RTL design • Apply constraints • Generate and interpret reports (area, power, timing)

Day 9: STA Lab (8 hrs) • Hands-On: • Perform full STA on synthesized design • Insert and analyse CDC violations • Debug and apply fixes using SDC edits

Day 10: Project + Review (8 hrs) • Hands-On Project: • Synthesize RTL for a given IP(RISC V Processor) • Perform complete STA • Create synthesis/STA scripts • Review results (area, power, timing).