Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.
Collaborate with a team of design and verification engineers to understand and verify the functionality of specific design elements within the context of the block, chip, and overall system.
Carefully document and execute test plans consisting of both directed and constrained-random tests to be run during simulation.
Adopt evolving verification methodologies used in the industry to functionally verify increasingly complex SoC designs under aggressive, market-driven schedules.
Work within the existing verification infrastructure on currently active projects.
5+ years of proven verification experience on large ASIC development projects or relevant software/firmware experience in a hardware development setting.
Strong background in:
PSS (Portable Stimulus Standard)
UVM (Universal Verification Methodology)
System Verilog
Experience in Verilog/System Verilog/SystemC preferred.
Experience with C/Verilog environments using DPI (Direct Programming Interface)/PLI (Programming Language Interface) preferred.
Strong analytical skills and high attention to detail.
Excellent written and verbal communication skills.
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