Creeno Solutions Pvt Ltd

Verification Engineer - Embedded System

Bengaluru, KA, IN

5 days ago
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Summary

Job Description

Key Responsibilities :

  • Define and implement power-aware verification strategy using UPF (IEEE 1801).
  • Integrate power intent into simulation environments and verify power management features.
  • Develop and maintain power-aware test benches and testcases in System Verilog/UVM.
  • Run simulations, debug failures, and ensure design functionality across power states.
  • Collaborate with RTL designers and architects to ensure correct power domain partitioning and isolation.
  • Perform static checks for power intent correctness using tools such as Synopsys VC LP or Cadence Conformal Low Power.
  • Ensure compliance of low-power implementation with overall chip power and performance goals.

Requirements

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of experience in ASIC/SoC verification with focus on low-power design.
  • Solid understanding of UPF 2.0/2.1/3.0 and power-aware verification methodologies.
  • Experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium) and waveform debugging tools.
  • Proficiency in System Verilog, UVM, scripting (Python/Perl/TCL).
  • Good understanding of power management techniques like power gating, clock gating, multi-voltage domains.

(ref:hirist.tech)

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