We are looking for an intern like you to be part of the team to work on our automation flow optimization.

Job Description:

• To investigate and optimize new tools & methodologies for the product quality & efficiency
  
  

Job Requirements:

• Understanding of design/verification languages such as, SystemVerilog, Verilog, UVM
• Familiar with Python, Shell or other scripting languages is a plus
• Knowledge of tools such as, RTL Simulators, e.g. VCS, Verdi
• Excellent written and verbal skills including Written and spoken English, Detailed status reporting
• The minimum contract term should be 6 months
• A bachelor’s degree in engineering is a minimum requirement
• Working in the office in Wuhan