Responsibilities: * SOC subsystem architect including documentation of micro-architecture * Lead design team for major subsystems of large SOCs Qualifications: * BS/MS degree with 10+ years of relevant work experience * Expert understanding of digital design and verification practices * Ability to write RTL based on a specification and simulate vectors to verify RTL * Experience using System Verilog (SV) and at least two prior RTL designs * Extensive knowledge of PCIe, USB3, or Power Delivery Experience: * Demonstrate an expert knowledge of System Verilog (SV) or similar verification language * Demonstrate an expert knowledge of Verilog for chip design and verification * Understanding the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and first silicon bring up and debug * Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.) * Experience with creating module level test benches and BFMs