Responsibilities

• Develop test plans, tests and coverage plans, as well as define verification methodology and testbenches.
• Develop verification environment to verify system can meet design requirements.
• Write test cases and execute test plans for complex designs.
• Close code/functional coverage for assigned designs under verification.
• Collaborate with teams across sites and geographies.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field of study.
• Knowledge of computer architecture and digital design fundamentals.
• Knowledge of UVM based verification methodologies.
• Knowledge of Verilog or SystemVerilog, digital simulation and debug.
• Ability to work independently to deliver the project goals.
• Excellent interpersonal skills and able to take on diverse challenges.