Note:

This position requires 3+ years of industrial experience in RTL Design.

Team and Role Overview

We are seeking a senior RTL Design Engineer to join our IC Design team. As a senior RTL Design Engineer, you will be responsible for and lead digital signal processing hardware designs, specifically data path as well as control intensive digital designs. You will work with or as the System architect, as well as other ASIC designers to micro-architect and implement low-power communication system designs integrated into our SoC.

Required Qualifications:

• Bachelor's degree in Science, Engineering, or related field.
• 3+ years ASIC design, verification, or related work experience.
• Strong skills in RTL logic design (VHDL or Verilog) and verification
• Should have extensively used RTL Linting tools and extensive usage of simulation tools.
• Experience with ASIC ECO flow, RTL sanity tools specific to Design Rule Checking and Clock Domain Crossing checks
• Familiarity with MBIST and DFT flow
• Gate level Simulation debug and usage of power extraction tools a plus

Preferred qualifications:

• Tcl/Perl/Python shell-scripting skills
• Experience with digital signal processing is a bonus
• Knowledge of different wireless communication circuits is a plus
• Outstanding communication and documentation skills
• Experience with multi-power domain design using UPF
• Power aware simulations using VCS-NLP or similar tools
• Experience using using STA, PNR tools
• Experience with Hardmacro integration in RTL

Who is a good fit

You will be considered for this position if you meet one of the following criteria:

● You have been a block/chip lead for digital blocks where the chip has performed as expected. Preferably the chip was an AMS chip rather than a processor.

● (OR) You have a 9/10 or higher GPA from one of the IITs, JU, VIT and possess a strong background in Digital Design