Client:

Our client a leading Multinational Semiconductor Company requires Senior Principal Digital Design SoC IP Verification Engineer for role based in Cork or Dublin, Ireland.

Role:

The group you will be joining develops and licenses IP for system designs. This includes CPUs and high-performance DSPs, DDR and IO controllers, hardware accelerators, and subsystems.

This group requires an experienced, motivated, Verification Engineer to join a new team. You will join a team implementing reference systems for Computer Vision, Machine Learning, Radar, Automotive, and other high- performance applications.

The group will also develop software and applications for reference systems and product demonstrations, highlighting the capability of subsystems and components.

Requirements:

This role requires extensive experience IP integration, and in designing and implementing SoC and compute-based systems. You will work closely with compute and interface IP development engineering and build designs to demonstrate the capabilities of subsystems and components.

Responsibilities:

• Design, develop and debug SoC reference systems.
• Develop subsystem testbench in System Verilog/UVM.
• Develop tests, scoreboards, checkers, coverage, etc. to verify subsystem.
• Integrate compute, memory and interface IP in system designs.
• Analyse IP products and implementation flows.
• Identify gaps and work with development teams to improve products.
• Develop collateral, and training material for system customers.
• Identify and implement best practices in hardware design, testing, and validation to improve efficiency and reliability.
• Stay up to date with latest industry trends, technologies, and design methodologies, and incorporate them into team’s workflows.

Experience

• BS in Electronic Engineering/Computer Science with 15+ years work experience, or MS in EE/CS with 8+ years experience.
• Must have at least 4 years of experience in ASIC design, integration, or verification teams.
• Must have expertise in some of the following domains: processor design, on-chip communication and interconnects, high-speed interfaces, or chiplets.
• Expertise in Verilog/System Verilog for coding and verification.
• Proficiency in RTL design techniques, including synthesis, timing closure, and verification.
• Experience in using UVM for functional verification of ASIC designs.
• Experience with EDA tools like Cadence and Synopsys for design simulation and verification.
• Extensive experience with FPGA emulation, design tools, and verification.

Contact:

For further information please contact Mícheál at Software Placements on 00353 1 5254642 or email [email protected]