Responsible for product design from system architecture and requirements allocation throughout product release and production of cost-sensitive, secure products
Analyze requirements, create test plans, build and set up scalable simulation environments from the ground up using SystemVerilog
Testing complex designs, code coverage, and functional coverage
Experience with OVM/UVM design verification, Bash, Perl, TCL, Python, and VHDL
🎯 Requirements:
Bachelor's degree and 8+ years of experience with subcontracts or contracts administration, or Master's degree plus a minimum of 6 years of relevant experience.
Active Secret clearance required
Location:
Dedham, MA - Relocation Available
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