A leading chip and silicon IP company is seeking a talented Senior Analog IC Design Engineer to join its Bufferchip Design team in Agoura Hills, California. This is an exciting opportunity to work alongside some of the brightest minds in the industry on innovative products that enhance data speed and security.
In this full-time role, the Senior Analog IC Design Engineer will report to the Senior Director of Engineering and play a key role in product definition and design. The position offers high visibility and cross-site collaboration across engineering teams.
Responsibilities
• Ownership of Analog designs at chip and/or block level
• Define optimal architectures to achieve competitive product specifications
• Design, simulate and characterize high-performance and high-speed circuits (e.g. Transmitter, Receiver, ADC, DAC, LDO, PLL, DLL, PI circuits).
• Create high level model for design tradeoff analysis and behavior model for verification simulations
• Create floorplan and work with layout team to demonstrate post extraction performance
• Document analysis and simulation to show that design achieves critical electrical, timing parameters and pre-silicon verification flow
• Work with the Lab/System team for test plan, silicon bring up and characterization
• Understand and disseminate applicable standards and its relevance in a given project to the team
• Mentor junior designers
Qualifications
• MS EE and 5+ years or PhD EE and 2+ years’ experience of CMOS analog circuit design. Position may be tailored appropriately with different level of experience.
• Prior experience in at least one of the following circuits: Transmitter, Receiver (with CTLE, DFE), PLL, DLL, PI, clock distribution
• Good knowledge of design principles for practical design tradeoffs
• Fundamental knowledge of basic building blocks like bias, op-amp and LDO
• Experience in designing memory interfaces such as DDR 4/5 or serial links such as PCIE is highly desirable
• Prior design experience in FinFET process and digitally assisted design is desirable
• Experience in modeling with matlab, Verilog-A, verilog is desirable
• Experience working in leading R&D and future technology development projects is desirable
• The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams
Location: Agoura Hills, CA (Hybrid)
Type: Fulltime
Salary Range: $166,000-196,000 (DOE)