Position: RTL Design Engineer

JOB Requirements:

• Working on SOC IP delivery with all sanity checks.
• Collaborate with implementation to achieve your timing and area.
• Working on LINT, CDC flows and analysis.
• Work on timing debug and closure.
• Drive the timely development and debug of new features on the custom memory controller.
• Produce quality RTL on schedule meeting PPA goals.

Responsibilities:

• Knowledge of memory controller.
• Experience in memory technologies: DDR4/5, LPDDR and HBM.
• Knowledge of Verilog, scripting, STA.
• Knowledge of PHY design.
• Energetic, curiosity, and passion in logic design.
• Knowledge of JEDEC memory standards.
• Good written and verbal communication skills

Regards,

Karthik Kumar

[email protected]