Responsibilities

• Design and maintain standard cells for new products based on new technology.
• Characterize the performance of standard cells and optimize the standard cell design and layout.
• Characterization and modeling of Standard Cell and semi-Custom cells to provide timing/power model for verification.
• Quality Analysis of characterized liberty models in terms of Timing, Power and Functionality.
• Closely collaborate with DTCO team to work on std cells architecture for emerging technologies.
• Develop automation test bench/flow/tools to improve the work efficiency and help data analysis.
• Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design.

Requirements

• Good understanding of CMOS circuit design
• Good knowledge of CMOS device physics and layout
• Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred.
• Experience in Primetime, Solido Analytics, ICC flow is added an advantage.
• Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision
• Experience in Standard Cell design and verification
• Experience in using Skill, TCL, Perl, Python to do test bench automation and data analysis is a plus
• Previous work experience in DRAM memory related fields or analog blocks is a plus.
• Must possess good interpersonal & communication skills and ability to work well in a team

Experience : 10 to 18 years

Education : BE/M.Tech