Principal Digital Design Engineer

A premier chip and silicon IP provider focused on accelerating and securing data is seeking an exceptional Principal Digital Design Engineer to join its Memory Interface Chip (MIC) team in San Jose, CA. This is an exciting opportunity to work alongside some of the industry’s most innovative engineers on cutting-edge technology that drives faster and more secure data solutions.

In this full-time role, the Principal Digital Design Engineer will report directly to the Senior Director of Analog Engineering and play a key role in the development of MIC products. The engineering team is focused on advancing DIMM Interface Chips, and this position will be central to driving progress on PMIC, TS, and SPD initiatives.

Responsibilities:

• Work with analog/digital design team for new product development
• Responsible for digital architecture design, RTL coding, functional simulation, analog-block Verilog model, post-pr simulation
• Support bench test, support ATE test
• Support chip bringing-up, debugging, failure analysis, characterizations and product release efforts
• Micro-controller firmware initial development

Requirements:

• Master degree or above in EE or related field
• At least 7 years of digital IC design experience
• Experience in the area listed below:
• Embedded SRAM/OTP/Efuse/MTP controller
• Design for test for digital block, analog block
• Communication bus such as I2C/I3C/SPI/AHB/APB
• Logic equivalent check
• Static timing check
• Familiar to schematic editor
• Micro-controller firmware development experience is a plus
• Being Familiar to mixed signal design and backend is a plus
• Mass product experience is a plus
• Self-motivated and proactive
• Good communication skills and a strong team player