Power, Modeling, Test and System Engineer (PMTS)

Low Power Systems

Location: Shanghai OR Beijing，China

Salary: $300,000 - $700,000 annually

About Us

We are a leading AI compute chip design and development team dedicated to creating cutting-edge solutions that push the boundaries of performance and energy efficiency. Our team combines expertise in architecture, software, hardware, and systems to deliver innovative products that excel in the AI chip market. We pride ourselves on having one of the most advanced power architecture capabilities in China and are committed to continuous innovation and excellence.

Role Overview

As a Power, Modeling, Test and System Engineer (PMTS), you will play a critical role in the design, optimization, and validation of our AI compute chips. You will work closely with architects, designers, and engineers to ensure that our products achieve superior performance and power efficiency. This position offers a unique opportunity to contribute to groundbreaking projects and shape the future of AI compute technology.

Key Responsibilities

- Power Architecture Design: Define performance and power targets for AI compute chips, design power-efficient architectures, and implement power-saving features to maximize energy efficiency.

- Performance-Power Modeling: Create and maintain models to simulate and predict power and performance behavior under various operating conditions. Perform joint analysis and evaluation of performance-power trade-offs.

- Optimization Strategy Development: Develop and implement optimization strategies to improve power efficiency and performance, leveraging advanced techniques such as dynamic voltage and frequency scaling (DVFS), power gating, and clock gating.

- Cross-Functional Collaboration: Work closely with Power Integrity, Packaging, and Post-Silicon teams to address design challenges and ensure seamless integration of power architecture into the overall chip design.

- Test Strategy Development: Design and execute test strategies to validate chip functionality, performance, and reliability. Analyze test results and collaborate with design teams to resolve issues.

- System Validation: Validate chip performance and functionality at the system level, ensuring that our products meet or exceed customer expectations in real-world applications.

- Innovation and Methodology: Contribute to the continuous improvement of our power architecture methodology, tools, and platforms. Explore new power management techniques and features to maintain our competitive edge.

Qualifications

- Education: Master’s or Ph.D. in Microelectronics, Computer Science, or a related field.

- Experience: Minimum of 5 years of experience in power architecture, performance modeling, test strategy, or related fields. Experience with advanced process node tape-out is highly preferred.

- Technical Skills:

- Proficiency in power architecture design and optimization techniques.

- Strong understanding of performance-power modeling and analysis tools.

- Knowledge of power integrity, packaging, and post-silicon validation.

- Experience with GPU, AI accelerator, or high-performance compute chip architectures.

- Familiarity with high-speed memory and interconnect technologies.

- Soft Skills:

- Excellent communication and collaboration skills.

- Strong problem-solving abilities and innovative mindset.

- Ability to work effectively in a fast-paced, cross-functional environment.

Why Join Us?

- Innovative Environment: Be part of a team at the forefront of AI compute chip innovation.

- Competitive Compensation: Attractive salary package with opportunities for growth and recognition.

- Professional Development: Continuous learning and development opportunities to advance your career.

- Impactful Work: Contribute to products that drive the future of AI and compute technology.

If you are passionate about power architecture, performance modeling, and system validation, and want to make a significant impact in the AI chip industry, we would love to hear from you!

Apply today to join our dynamic team in Shanghai Shanghai OR Beijing China.