Job Description:

We are seeking an experienced and highly skilled Block-Level Design Engineer to join our innovative team. The ideal candidate will excel in RTL-to-GDSII design processes and demonstrate expertise in advanced implementation tools and techniques. This role offers an opportunity to work on cutting-edge designs for lower nodes (3nm, 4nm, 5nm).

Key Responsibilities:

• Perform block-level design tasks, progressing from RTL-to-GDSII.
• Execute synthesis, floor-planning, place & route, timing/EMIR/PV closure, and final signoff processes.
• Demonstrate proficiency in the Cadence Implementation tool suite (Genus, Innovus).
• Implement and optimize controllers for High-Speed IO IPs.
• Conduct structural implementation, including datapaths, bus planning, and routing strategies.
• Design and manage systems with multi-power domains.
• Develop and maintain scripts for design workflows using TCL and Python.

Requirements:

• Extensive experience with Cadence Implementation tools (Genus, Innovus).
• Proven expertise in structural implementation involving datapaths, bus planning, and routing.
• Strong scripting abilities using TCL and Python.
• Familiarity with multi-power domain design methodologies.
• Experience in designing and implementing controllers for High-Speed IO IPs.
• Knowledge of lower-node technologies (3nm, 4nm, 5nm) is a strong advantage.