Qualifications

• Hands-on tape-out experience performing timing and physical verification closure on 5nm FinFET TSMC process or similar/lower technology nodes
• Hands-on experience with block level physical design (Floorplanning to GDSII)
• Experience with SoC level integration (multiple blocks, SoC floorplan, clocking, and timing analysis) preferred
• Expertise in Cadence (Innovus) P&R, Synopsys PrimeTime/StarRC/ICV, Ansys Redhawk, and Mentor Graphics Caliber EDA tools
• Proficiency in scripting languages, such as Makefiles, Tcl, Unix Shell, Python
• Hands-on experience in writing scripts to improve or develop flow from scratch
• Solid engineering understanding of the underlying concepts of IC design, implementation flows, and methodologies for deep submicron design
• 10+ years industry experience, BS EE

Responsibilities

• Block level floorplanning and physical design activities for one or more blocks
• Block level physical design includes floorplan, power plan, placement, CTS, timing analysis, and route optimization
• Signoff timing and physical verification closure
• Ensure the floorplan is optimal, congestion issues are resolved, and timing is under control at every stage from synthesis, placement, CTS, and route stages
• Timing closure with crosstalk and OCV under Multi-Mode Multi-corner conditions
• Noise signoff
• Physical verification including LVS, DRC, Antenna, and IR closure
• Flow development/automation