Job Details:-
Job Title: Physical Design Engineer(SoC)
Duration: 06 Months
Location: San Jose, CA 95134 – Hybrid 3 Days a week
Pay Range: $75 - $85/hour on W2
Job Description:
We are looking for a results-oriented Physical Design Engineer(Contractor) to join our design team. You will be working on the physical design of leading edge designs supporting mobile applications. The role and responsibility includes taking the design from synthesized gates to delivery of GDS for tapeout. To ensure success as a physical design engineer, you should demonstrate extensive knowledge of place and route and tapeout session. Must have 5+ years latest experience on Synopsys physical design tool, ICC2 experience Strong Place and route skills Strong technical knowledge and tapeout experience - Need to handle multiple blocks for 28nm, 14nm and 8nm Strong Calibre DRC/LVS experience Experience with Star-RC extraction Working on timing and functional ECO Hands-on experience with low-power implementation experience. TCL scripting skills - Good debugging skills and find a workaround for tool issues. Developing codes, as well as maintaining layout automation features and macros in layout entry tools.
Requirements
What You Bring
5+ years of experience in a related field. Bachelor’s degree in computer engineering, Electrical engineering or related field. You’re inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change.
Description:
• Perform physical implementation in Synopsys tools (ICC2)
• Develop and maintain the tool flow to support the project.
• Work with Team to enhance PD methodology.
• Fixing DRC/LVS issues
• Fixing voltage drop violations
• Timing ECOs
Requirements:
• Experience in advanced node processes 16nm and below. • Experience with industry-standard tools, preference for Synopsys flow. • Understanding of Implementation flow · Understanding of timing constraints and static timing analysis (STA). • Experience with Calibre for DRC/LVS checks, and automation through scripting such as Perl, Python, Tcl & Make.