Physical Design - JD

Experience: 2-20 yrs

• Strong background of ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.
• Hands-on experience on technology nodes like 7nm, 14nm, 10nm.
• Good knowledge of EDA tools from Synopsys , Cadence and Mentor
• Hands-on experience in floor planning, placement optimizations, CTS and routing.
• Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS)
  
  

Skills:- Static timing analysis, Application Specific Integrated Circuit (ASIC), Floorplan Manager, Extraction, Synopsys and Physical Design