PD Job Scope

EXPERIENCE - 5-8 Years

• Block level floor planning, pre-wire and timing-optimization tasks
• Detailed place and route for both block macros and chip level, including clock-tree-synthesis, power routing, timing driven placement and routing, signal integrity analysis, and design for yield techniques
• Generation of detailed parasitic information
• Static and Dynamic rail analysis
• Signoff Static Timing Analysis
• Physical verification, including LVS and DRC