Company Description

NXP is a world leader in secure connectivity solutions for embedded applications, driving semiconductor innovation in automotive, industrial & IoT, mobile, and communication infrastructure markets. Headquartered in Eindhoven, Netherlands, NXP operates in over 30 countries with one of the largest R&D Design centers in India, employing more than 2500 engineers across Noida, Bangalore, Hyderabad, and Pune. NXP India engineers work on cutting-edge technologies, developing innovative solutions across business lines such as Advanced Analog, Automotive Processing, Connectivity & Security, Edge Processing, and Radio Frequency Processing. With more than 50 years of presence, NXP India is among the most innovative teams globally.

Role Description

This is a full-time on-site role located in Noida /Bangalore for a Sr.Principal / Principal/ Lead Design Verification Engineer. The Verification Engineer will be responsible for leading and executing formal and functional verification tasks, RTL design, and debugging activities with expertise in RTL and Gate-Level Simulation (GLS) for SDVs, Automotive Zonal Controllers and futuristic AI on Edge devices . The engineer will work closely with other design and verification teams to ensure the quality , functionality and performance of the SoC .The ideal candidate will have a strong background in pre-silicon and post-silicon debugs, ensuring high-quality and functionally safe designs for next-generation automotive and industrial applications.

Key Responsibilities

• Develop and execute verification plans for SDVs, automotive zonal controllers and edge devices.
• Perform RTL and GLS verification, including debugging timing-related issues.
• Create and enhance UVM-based testbenches for scalable and reusable verification.
• Work closely with design, system, and firmware teams to validate system-level functionality.
• Ensure compliance with automotive safety standards (ISO 26262) and low-power verification methodologies.
  
  

Requirements

• 8-18 years of experience in ASIC/FPGA verification.
• Expertise in UVM, SystemVerilog, and constrained random verification.
• Strong understanding of RTL design, synthesis, STA, and GLS debugging.
• Experience with automotive SoCs, communication protocols (CAN, LIN, Ethernet, PCIe), and functional safety (ISO 26262, ASIL levels).
• Hands-on experience with power-aware verification and mixed-signal verification is a plus.
• Experience with scripting languages like Python, Perl,
  
  

(ref:hirist.tech)