System Level Modelining Engineer

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore (WFH )

A US based well-funded product-based startup looking for Highly talented Verification Engineers for the following roles.

Number of positions - 2 (Hyderabad only)

Responsibilities:

• System Level Modelling for Architecture exploration, Performance exploration, SoC performance analysis, trade-offs analysis
• C++/SystemC model development for various abstractions ranging from Loosely Timed, Cycle Approximate to Cycle Accurate abstraction levels
• Models for architectural components like Memory subsystem, Bus Interconnect, Peripheral models, multi-core SoC platforms using C++/SystemC, TLM
• Performance analysis of developed models using SPEC-HPC, SPEC-CPU benchmarks etc.
• Design and develop design algorithms in C++/SystemC for efficient HW implementation

Key Qualifications:

• 2+ years' experience in performance modelling using C++/SystemC, TLM2.0, Extending TLM2.0
• Proficiency in C++/SystemC , OOPS, STL, data structures, algorithms, and programming concepts
• Exposure to any HDL: SystemC, Verilog, System Verilog, VHDL
• Understanding of Microprocessor, Microcontrollers, SOC architecture, bus protocols etc.
• Familiarity with industry standard benchmarks such us SPEC-HPC, LLAMA, SPEC-CPU etc
• Familiarity with Memory architectures, Memory Controller architectures, Cache, MMU, Virtual Memory, TLB, processes
• Knowledge of system bus (AMBA, OCP, NoC) and memory protocols (LPDDR5/LPDDR6/HBM4) is plus.

Contact:

Uday

Mulya Technologies

[email protected]

"Mining The Knowledge Community"

Contact:

Uday

Mulya Technologies

[email protected]

"Mining The Knowledge Community"